Semiconductor device, power amplifier device and PC card

ABSTRACT

The present invention is directed to improve high frequency characteristics by reducing inductance of a source. In an HEMT assembled in a power amplifier device, each of a drain electrode, a source electrode, and a gate electrode is constructed by a base portion and a plurality of fingers projected in a comb-teeth shape from the base portion, and the fingers of the electrodes mesh with each other. In the source electrode, a width of the fingers positioned at both ends of the plurality of fingers is wider than a width of each of the fingers positioned between both ends. The width of each of the fingers positioned at both ends is a width equal to or larger than a sum of the widths of the plurality of fingers positioned between both ends, and the width of the base portion is wider than that of each of the fingers positioned at both ends. An electrode pad provided for the source base portion and an external electrode terminal are connected to each other via a conductive wire.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device, a poweramplifier device, and a personal computer (PC) card and, for example, toa technique effectively applied to manufacturing of a PC card for awireless LAN.

[0002] As penetration of personal computers to offices and homesincreases, communication between personal computers typified by theInternet is being actively performed. Attention is being paid to awireless LAN (local area network) for performing the communicationbetween personal computers wirelessly, not by wire. At present, awireless LAN conformed to the 2.4-GHz band “IEEE (The Institute ofElectrical and Electronics Engineers, Inc.) 802.11b” standard is in themainstream. However, since the transmission speed is 8 Mbps at themaximum and is low, it causes a problem that a moving image cannot betransmitted. One of solutions to the problem is a wireless LAN of the 5GHz band “IEEE802.11a” standard enabling the maximum transmission speedof 54 Mbps.

[0003] In a PC card for use in the wireless LAN, an antenna, atransmission/reception change-over switch, a low-noise amplifier forreception, a mixer for reception, a mixer for transmission, a poweramplifier for transmission, and the like are assembled.

[0004] Semiconductor devices of high frequencies such as a few GHz (forexample, an HEMT (High Electron Mobility Transistor), an MMIC(Monolithic Microwave IC), and the like) are formed on the basis of acompound semiconductor substrate such as a GaAs substrate.

[0005] On the other hand, in a field effect transistor (FET) to increasethe performance of a device in a high frequency band, for example, inplace of a configuration of connecting a source electrode on the topface of a semiconductor chip and a source terminal of a packagesubstrate via a wire, a via hole penetrating a semiconductor chip isprovided, a conductor is formed in the via hole, the source electrode onthe top face of the semiconductor chip is led to the under face of thesemiconductor chip and, when the semiconductor chip is fixed to thepackage substrate, the led source electrode is directly connected to thesource terminal of the package substrate (seating), thereby achievingreduction in the source inductance (refer to, for example, PatentReference 1).

[0006] As a power amplifier for transmission (power amplifier device fortransmission) in a mobile communication system, there is a module or anintegrated circuit (MMIC) using a GaAs-MESFET or a heterojunctionbipolar transistor (HBT) (for example, Patent Reference 2).

[0007] [Patent Reference 1]

[0008] Japanese Unexamined Patent Publication No. Hei 8 (1996)-330568,pp. 2-3, FIG. 1

[0009] [Patent Reference 2]

[0010] Japanese Unexamined Patent Publication No. Hei 11(1999)-220344,pp. 2-5, FIGS. 1 and 8

SUMMARY OF THE INVENTION

[0011] A power amplifier for transmission assembled in a PC card for usein a wireless LAN is manufactured by use of a compound semiconductor(for example, GaAs) in order to realize a high frequency characteristicin an ultra high frequency band of 5 GHz. Generally, a power amplifierhaving a multi-stage amplification configuration in which transistorssuch as GaAs-MESFETs, HEMTs, HBTs, and the like formed on a GaAssubstrate are cascaded in a number of stages is manufactured.

[0012] To realize smaller size and lighter weight, the mounting area ofsuch a power amplifier is reduced. From the viewpoint of reduction inthe number of parts to realize cost reduction as the customer needs, itis indispensable to form the power amplifier as an MMIC.

[0013] Techniques effective to realize formation of an MMIC includes (1)a via hole technique enabling higher performance by reducing a sourceinductance in an FET, (2) a high-density high-capacity techniquerealizing reduction in the capacity area by increasing capacity anddensity in the case of using an MIM (Metal-Insulator-Metal) capacitor asa capacitor in a matching circuit (input, inter-stage, and outputmatching circuit), and (3) a circuit optimizing technique for chip sizereduction.

[0014] To form a via hole (having a diameter of, generally, about 50μm), a new mask has to be added and the cost increases. For formation ofa via hole, a thinner substrate (up to about 70 μm) and a high-precisionback face processing technique are required. Consequently, there areproblems such as increase in the number of processes and difficulthandling.

[0015] As a measure to avoid the problems, a conventional configurationof the power amplifier using no via holes may be considered.

[0016]FIG. 16 is a plan view showing a comb-shaped electrode structurehaving a comb-teeth shaped electrode in a conventional FET. Each of asource electrode, a drain electrode, and a gate electrode has acomb-teeth shaped electrode pattern constructed by a base portion and aplurality of fingers extending from the base portion. Fingers 51 b, 52b, and 53 b of a source (S) electrode 51, a drain (D) electrode 52, anda gate (G) electrode 53 are disposed so as to mesh with each other on achannel region 50. Specifically, the gate finger 53 b is positionedbetween the source finger 51 b and the drain finger 52 b. Width W1 ofthe source finger 51 b and width W4 of the drain finger 52 b are thesame. To reduce the source inductance, it is necessary to enlarge thearea (L×W2) of the base portion (source base portion) 51 a of the sourceelectrode 51 and increase the number of conductive wires connected tothe base portion 51 a.

[0017]FIG. 17 is a schematic plan view showing an example of asemiconductor chip constructing an amplifier by use of the FET of FIG.16, that is, an MMIC chip. This MMIC chip (semiconductor chip) 60 has aconfiguration including an amplifier in one stage. Depending on theamplification factor, FETs are cascaded in a number of stages.

[0018] In FIG. 17, two FETs 61 and 62 each having the conventional FETstructure shown in FIG. 16 operate in parallel, thereby increasing anoutput. The FET 61 has a source electrode 51′, a drain electrode 52′,and a gate electrode 53′. Source fingers 51 b′, drain fingers 52 b′, andgate fingers 53 b′ are disposed so as to mesh with each other on achannel region 50′. Specifically, a mesh pattern is formed such that thegate finger 53 b′ is positioned between the source finger 51 b′ and thedrain finger 52 b′. A source base portion 51 a′ is provided with aplurality of (six) square-shaped electrode pads 51 c′. To the electrodepads 51 c′, conductive wires connected to the source terminals of anow-shown package are connected.

[0019] The FET 62 has a source electrode 51″, a drain electrode 52″, anda gate electrode 53″. Source fingers 51 b″, drain fingers 52 b″, andgate fingers 53 b″ are disposed so as to mesh with each other on achannel region 50″ in a manner similar to the FET 61. The source finger51″ is provided with a plurality of (six) square-shaped electrode pads51 c″. To the electrode pads 51 c″, conductive wires connected to thesource terminals of a now-shown package are connected.

[0020] On the top face of the MMIC chip 60, as electrode pads, anelectrode pad 65 for input, an electrode pad 66 for output, an electrodepad 67 for first power source voltage, an electrode pad 68 for secondpower source voltage, and an electrode pad 69 for third power sourcevoltage are provided.

[0021] The gate electrodes 53′ and 53″ of the FETs 61 and 62 areconnected to each other via strip lines 70′ and 70″ for a matchingcircuit. Between a connection node 71 and the electrode pad 65 forinput, an MIM capacitor 72 is electrically connected. Between theconnection node 71 and the electrode pad 69 for third power sourcevoltage, a spiral inductance 73 is electrically connected.

[0022] The drain electrodes 52′ and 52″ of the FETs 61 and 62 areconnected to a wire 80. Between the wire 80 and the electrode pad 66 foroutput, an MIM capacitor 81 is electrically connected. The wire 80 andthe electrode pad 67 for first power source voltage are electricallyconnected to each other via a strip line 82 for a matching circuit.Between the MIM capacitor 81 and the electrode pad 68 for second powersource voltage, a spiral inductance 83 is electrically connected.

[0023] In the structure, to make the inductance of the source electrodeclose to the inductance in the case of the via hole, the number of wiresconnected (metal lines each having a diameter of 25 μm) is set to themaximum number of six.

[0024] In such a structure, however, reduction in the source inductanceis small. In the case of reducing the source inductance by increasingthe number of wires, the chip size has to be increased by increasing thenumber of electrode pads (bonding pads). That is, the number of wires isspecified by the size of the semiconductor chip.

[0025] The inventor herein has therefore analyzed and examined reductionin inductance in accordance with an electrode pattern in a state wherethe number of wires is set to the maximum and, as a result, achieved thepresent invention.

[0026] An object of the invention is to provide a semiconductor devicewith reduced inductance of an earth electrode.

[0027] Another object of the invention is to improve high frequencycharacteristics of a power amplifier device.

[0028] Further another object of the invention is to reduce themanufacturing cost of a power amplifier device.

[0029] Further another object of the invention is to provide a personalcomputer card having excellent high frequency characteristics.

[0030] The above and other objects and novel features of the inventionwill become apparent from the description of the specification and theattached drawings.

[0031] An outline of a representative one of inventions disclosed in thespecification will be briefly described as follows.

[0032] (1) A personal computer card having a power amplifier device fortransmission connected to an antenna, wherein the power amplifier devicefor transmission has one or a plurality of amplification systems, theamplification system has a semiconductor chip in which a transistor(FET) is formed and a plurality of external electrode terminals, theexternal electrode terminals are an input terminal to which a signal tobe amplified is supplied, an output terminal for outputting theamplified signal, and first, second, and third power source terminals,two transistor are electrically connected in parallel between the inputterminal and the output terminal, electrodes of the transistor are acontrol electrode (gate electrode) connected to the input terminal andthe third power source terminal, a first electrode (drain electrode)connected to the output terminal and the first power source terminal,and a second electrode (source electrode) connected to the second powersource terminal serving as an earth terminal, on the top face of thesemiconductor chip, an electrode pad corresponding to the externalelectrode terminal and a plurality of electrode pads formed in theportion of the second electrode of the transistor are provided, aconductive wire for electrically connecting the external electrodeterminal and the electrode pad corresponding to the external electrodeterminal, and a conductive wire for electrically connecting theplurality of electrode pads formed in the portion of the secondelectrode of the transistor and the second power source terminal areprovided, each of the electrodes of the transistor is constructed by abase portion and a plurality of fingers projected in a directionorthogonal to the base portion, one of the fingers of the firstelectrode (drain electrode) is disposed between two neighboring fingersof the second electrode (source electrode), the second electrode isconnected to a fixed potential, and the width of each of the fingerspositioned at both ends of the second electrode (source electrode) iswider than the width of each of the fingers positioned between the bothends. The width of each of the fingers positioned at both ends in thesource electrode is equal to or wider than a sum of widths of theplurality of fingers positioned between the both ends, and the width ofthe base portion of the second electrode is wider than the width of eachof the fingers positioned at both ends.

[0033] The power amplifier device also includes: a supporting substrateon which the semiconductor chip is mounted and constructing the secondpower source terminal; a plurality of leads disposed around thesupporting substrate and constructing the external electrode terminals;and a sealing part made of an insulating resin for covering thesupporting substrate, the external electrode terminal, the semiconductorchip, and the wire in a state where an under face and an external endface of each of the supporting substrate and the external electrodeterminal are exposed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034]FIG. 1 is a schematic plan view of an MMIC chip to be assembled ina power amplifier device as an embodiment (first embodiment) of theinvention.

[0035]FIG. 2 is a partly-cutaway schematic plan view of the poweramplifier device.

[0036]FIG. 3 is a bottom view of the power amplifier device.

[0037]FIG. 4 is a cross section of the power amplifier device.

[0038]FIG. 5 is an equivalent circuit of the MMIC chip.

[0039]FIG. 6 is a schematic cross section showing an HEMT part, an MIMcapacitor part, and a spiral inductance part of the MMIC chip.

[0040]FIG. 7 is a schematic enlarged cross section showing the HEMTpart.

[0041]FIG. 8 is a schematic enlarged cross section showing the MIMcapacitor part and the spiral inductance part.

[0042]FIG. 9 is an equivalent circuit diagram of the MIM capacitor.

[0043]FIG. 10 is a schematic plan view showing an electrode pattern ofthe HEMT.

[0044]FIG. 11 is a schematic diagram showing a drain current path in theHEMT.

[0045]FIG. 12 is a block diagram showing a functional configuration of awireless LAN PC card in which the power amplifier device of the firstembodiment is assembled.

[0046]FIG. 13 is a schematic plan view showing the appearance of thewireless LAN PC card.

[0047]FIG. 14 is a schematic plan view showing an electrode pattern ofan HBT in an MMIC chip assembled in a power amplifier device as anotherembodiment (second embodiment) of the invention.

[0048]FIG. 15 is a schematic enlarged cross section taken along lineA-A′ of FIG. 14.

[0049]FIG. 16 is a schematic plan view showing an example of theelectrode pattern of a conventional FET.

[0050]FIG. 17 is a schematic plan view showing an electrode pattern ofan HEMT in an MMIC chip assembled in a conventional power amplifierdevice.

DETAILED DESCRIPTION OF THE PREFERRED

[0051] Embodiments of the invention will be described in detailhereinbelow with reference to the drawings. In all of the drawings forexplaining the embodiments of the invention, the same reference numeralis given to components having the same function and repetitivedescription will not be given.

[0052] (First Embodiment)

[0053] FIGS. 1 to 13 are diagrams related to a semiconductor device, apower amplifier device, and a personal computer card of a firstembodiment. FIG. 1 is a diagram related to a semiconductor device (MMICchip). FIGS. 2 to 11 are diagrams related to a power amplifier device.FIGS. 12 and 13 are diagrams related to a personal computer card.

[0054] A high frequency part of a personal computer (PC) card 1 for usein a wireless LAN has a reception system and a transmission system asshown in the block diagram of FIG. 12. The reception system includes anantenna 2, a transmission/reception change-over switch (SW) 3 to whichthe antenna 2 is connected, a low-noise amplifier (LNA) 4 for receptionconnected to the transmission/reception change-over switch 3, a mixer(Rx-Mix) 5 for reception connected to the low-noise amplifier 4 forreception, and a base band LSI 6 connected to the mixer 5 for reception.The transmission system includes the base band LSI 6, a mixer (Tx-Mix) 7for transmission connected to the base band LSI 6, a power amplifierdevice 10 for transmission connected to the mixer 7 for transmission,the transmission/reception change-over switch 3 connected to the poweramplifier device 10, and the antenna 2. A voltage controlled oscillator11 is connected to the base band LSI 6, mixer 5 for reception, and mixer7 for transmission. Although not described in detail, two antennas areprovided to improve sensitivity in a diversity configuration.

[0055] The personal computer card 1 has a thin flat card structure asshown in FIG. 13. At one end of the personal computer card 1, aconnector 12 is provided. When the personal computer card 1 is insertedinto a card slot of a personal computer, the connector 12 iselectrically connected to the personal computer. The antenna is built ina casing 13 of the personal computer card 1. The personal computer card1 is a personal computer card for a wireless LAN conformed to the “IEEE802.11a” of the 5-GHz band enabling the maximum transfer speed of 54Mbps.

[0056] For use in the ultra high frequency band of 5 GHz, each of theparts assembled in the personal computer card is requested to havehigh-level high frequency characteristics. Among the parts, the poweramplifier device (high output power amplifier or high frequency poweramplifier) is an important component. A high gain, a high output, and alow distortion characteristic are required, and low cost is alsodemanded.

[0057] The power amplifier device 10 for transmission will now bedescribed. FIGS. 2 to 4 are diagrams related to the power amplifierdevice 10. FIG. 2 is a partly-cutaway schematic plan view of the poweramplifier. FIG. 3 is a bottom view, and FIG. 4 is a cross section.

[0058] As shown in FIGS. 2 to 4, the power amplifier device 10 has athin flat square shape, and the top and side faces are formed by sealingparts 15 made of an insulating resin. In the under face (mounting face)of the sealing part 15, the under face of a square-shaped supportingsubstrate (TAB tape) 17 supported by thin TAB-tape supporting leads 16is exposed. As shown in FIGS. 2 and 3, the TAB-tape supporting leads 16extend along diagonal lines of the square on the under face of thesealing part 15. On the outside of each of the sides of the TAB tape 17,a plurality of leads 18 are disposed. Between the neighboring TAB-tapesupporting leads 16, although not particularly limited, three leads 18are disposed parallel to each other.

[0059] As shown in FIGS. 2 and 4, a semiconductor chip 20 is fixed tothe top face of the TAB tape 17 by an unshown adhesive. As shown in FIG.2, electrode pads 21 provided on the top face of the semiconductor chip20 and the predetermined leads 18 are electrically connected to eachother via conductive wires 22. As the wire 22, for example, a metal linehaving a diameter of 25 μm is used.

[0060] As shown in FIGS. 3 and 4, the sealing part 15 made of aninsulating resin is formed on the top face side of the TAB tape 17 andthe lead 18. The sealing part 15 completely covers the semiconductorchip 20 and the wires 22. The top face of the sealing part 15 is a flatface. As shown in FIG. 4, the under faces of the TAB tape 17, TAB-tapesupporting leads 16, and leads 18 are exposed from the under face of thesealing part 15, and the outer end faces of the lead 18 and the TAB-tapesupporting leads 16 are flush with the peripheral face of the sealingpart 15 and exposed in the peripheral face of the sealing part 15. Thatis, the power amplifier device 10 of the first embodiment is a so-callednon-lead type semiconductor device such that leads do not project fromthe peripheral face of the sealing part 15. Since the sealing part 15has a square shape, the power amplifier device 10 has a QFN structure.

[0061] In manufacture of the power amplifier device 10, a lead framemade of a metal is used. The lead frame is obtained by forming a thinflat metal plate in a desired pattern by etching or press. A single leadpattern includes a square-shaped frame. In the frame, the TAB tape, theTAB tape supporting leads, and the leads are provided. The lead and theTAB tape supporting lead extend so as to project from the innercircumferential face of the frame to the inside. In the lead frame, alead pattern is arranged in one line or a few lines, and product formingparts by the lead pattern are disposed in one line or a matrix.

[0062] In manufacture of the power amplifier device, the semiconductorchip 20 is fixed (mounted) on the top face of the TAB tape 17 of each ofproduct forming parts via an unshown adhesive by performing chipbonding. After that, by performing wire bonding, the electrode pad 21 onthe top face of the semiconductor chip 20 and an inner end part of thelead 18 are connected via the conductive wire 22. Subsequently, byperforming transfer molding, an insulating resin layer having apredetermined height is formed on the top face side of the lead frame.By performing dicing to separate the lead frame and the insulating resinlayer from each other, the power amplifier device 10 shown in FIGS. 2 to4 is manufactured.

[0063] In the transfer molding, a lead frame is sandwiched between alower-half die and an upper-half die of a transfer molding apparatus,and a resin is charged into a cavity formed by the upper-half andlower-half dies, thereby forming an insulting resin layer. Since theunder face of the lead frame is placed on a flat surface (partingsurface) of the lower-half die, the charged resin does not enter theunder surface of the lead frame. As a result, the under face of each ofthe TAB tape supporting lead 16, TAB tape 17, and lead 18 is exposed inthe under face of the insulating resin layer. Since the ceiling face ofthe cavity is formed flatly and is parallel to the parting surface ofthe lower-half die, the height of the insulating resin layer, that is,the sealing part 15 is constant as shown in FIG. 4. Since the lead frameand the insulating resin layer are diced by a dicing blade at the sametime, an external end face of each of the lead 18 and the TAB supportinglead 16 is flush with the circumferential face of the sealing part 15and is exposed to the circumferential face of the sealing part 15.

[0064]FIG. 1 is a schematic plan view of the semiconductor chip 20, thatis, an MMIC chip. FIG. 5 is an equivalent circuit of the semiconductorchip 20. The semiconductor chip 20 has, as shown in FIG. 1, a pluralityof electrode pads 21 on the top face. The electrode pads 21 are, asshown in FIG. 5, an input electrode pad (Pin) 25, an output electrodepad (Pout) 26, an electrode pad (Vdd) 27 for first power source voltage,an electrode pad (GND) 28 for second power source voltage, and anelectrode pad (Vgg) 29 for third power source voltage. As will bedescribed later, a plurality of electrode pads 21 are formed in each ofsource electrode parts as second electrodes of transistors.

[0065] The power amplifier device 10 of the first embodiment has aconfiguration in which, as shown in the equivalent circuit diagram ofFIG. 5, two transistors 31 and 32 are connected in parallel between theinput electrode pad (Pin) 25 and the output electrode pad (Pout) 26. Thetransistors 31 and 32 are HEMTs. A control electrode (gate electrode) asan input electrode of the transistors and a first electrode (drainelectrode) as an output electrode are connected to each other, and theconnection portions serve as connection nodes A and B. Between theconnection node A on the gate electrode side and the input electrode pad25, an MIM capacitor 33 is connected. Between the connection node A andthe electrode pad (Vgg) 29 for third power source voltage, an inductance34 is connected.

[0066] Between the connection node B on the drain electrode side and theoutput electrode pad (Pout) 26, an MIM capacitor 35 is connected. Aninductance 36 is connected between the MIM capacitor 35 and theelectrode pad (GND) 28 for second power source voltage. The drainelectrodes of the transistors 31 and 32 are connected to the electrodepad (Vdd) 27 for first power source voltage, and a potential Vdd isapplied to the drain electrode. For example, Vdd is 3.3V. The secondelectrode (source electrode) of the transistors 31 and 32 is connectedto the electrode pad (GND) 28 for second power source voltage.

[0067] At the electrodes of the transistors 31 and 32, the gateelectrode and the drain electrode are connected to the electrode pads 21via wires (to which numerals are not given) provided for thesemiconductor chip 20. In contrast, as shown in FIGS. 2 and 1, thesource electrode has a structure in which a part of the source electrodepattern has the plurality of electrode pads 21.

[0068] In a transistor, an input matching circuit, an output matchingcircuit, or a bias circuit is constructed by a capacitor, a resistor, aninductance, and the like. A microstrip line “m” shown by a rectangularportion in FIG. 5 is also a part of the circuits. The potential (Vgg)supplied as a bias potential from the electrode pad (Vgg) 29 for thirdpower source voltage is, for example, −1.0V.

[0069] Next, the semiconductor chip 20 having the MMIC structure will bedescribed. FIG. 1 shows the semiconductor chip 20 having a one-stageamplifier configuration. The invention is not limited to theconfiguration. In the case of obtaining a higher amplification factor, amulti-stage amplifier configuration in which transistors are cascaded ina number of stages is employed. Although the number of amplificationsystem is one, a plurality of amplification systems which can be usedwhile being switched by a change-over switch may be provided.

[0070] In the amplification system in the power amplifier device 10 ofthe first embodiment, as shown in FIG. 1, two transistors (HEMTs) areconnected in parallel between the input electrode pad (Pin) 25 and theoutput electrode pad (Pout) 26, thereby increasing the output.

[0071] The transistor 31 has a drain electrode 37, a source electrode38, and a gate electrode 39. Each of the electrodes is constructed by abase portion linearly extended and a plurality of fingers projected inthe direction perpendicularly crossing the base portion (a plurality offingers projected in a comb teeth shape from one end of the baseportion). Specifically, the drain electrode 37 is constructed by a drainbase portion 37 a and a plurality of drain fingers 37 b extended fromone end of the drain base portion 37 a. The source electrode 38 isconstructed by a source base portion 38 a and a plurality of sourcefingers 38 b extended from one end of the source base portion 38 a. Thegate electrode 39 is constructed by a gate base portion 39 a and aplurality of gate fingers 39 b extended from one side of the gate baseportion 39 a.

[0072] Each of the fingers extends so as to cross a channel region 40. Apattern is formed in which one of the fingers of a first electrode(drain electrode) is disposed between two neighboring fingers of asecond electrode (source electrode). In other words, the fingers of theelectrodes are arranged so as to mesh with each other. That is, a meshpattern such that the gate finger 39 b is positioned between the drainfinger 37 b and the source finger 38 b is formed. The source baseportion 38 a is provided with a plurality of (six) square-shapedelectrode pads 21. To the electrode pads 21, the wires 22 are connectedas shown in FIG. 2. The source electrode is connected to a fixedpotential.

[0073] The transistor 32 has a drain electrode 42, a source electrode43, and a gate electrode 44. Each of the electrodes of the transistor 32is constructed by a base portion extended linearly and a plurality offingers projected like a comb-teeth shape from one side of the baseportion. Specifically, the drain electrode 42 is constructed by a drainbase portion 42 a and a plurality of drain fingers 42 b extending fromone side of the drain base portion 42 a. The source electrode 43 isconstructed by a source base portion 43 a and a plurality of sourcefingers 43 b extending from one side of the source base portion 43 a.The gate electrode 44 is constructed by a gate base portion 44 a and aplurality of gate fingers 44 b extending from one side of the gate baseportion 44 a.

[0074] Each of the fingers extends so as to cross a channel region 45,and the fingers of the electrodes are arranged so as to mesh with eachother. That is, a mesh pattern is obtained such that the gate finger 44b is positioned between the drain finger 42 b and the source finger 43b. The source base portion 43 a is provided with a plurality of (six)square-shaped electrode pads 21. To the electrode pads 21, the wires 22are connected as shown in FIG. 2.

[0075] The gate electrodes 39 and 44 of the transistors 31 and 32 areconnected to each other and construct the connection node A as describedabove. The drain electrodes 37 and 42 of the transistors 31 and 32 areconnected to each other and construct the connection node B as describedabove.

[0076] As described above, the MIM capacitor 33 is connected between theconnection node A on the side of the gate electrodes and the inputelectrode pad 25, and the inductance 34 is connected between theconnection node A and the electrode pad 29 for third power sourcevoltage. The MIM capacitor 35 is connected between the connection node Bon the drain electrode side and the output electrode pad 26, and theinductance 36 is connected between the MIM capacitor 35 and theelectrode pad 28 for second power source voltage. To the drainelectrodes of the transistors 31 and 32, the electrode pad (Vdd) 27 forfirst power source voltage is connected, and the potential Vdd isapplied to the drain electrodes. Lines connected to the electrode pads21 and electrodes in FIG. 1 are wires and the microstrip lines m. InFIG. 2, to avoid complication of the drawing, reference numerals of thetransistors 31 and 32, the electrode pads 21, and the wires 22 connectedto the electrode pads 21 are shown but the other reference numerals areomitted.

[0077] In the power amplifier device 10, as shown in FIG. 2, theelectrode pads 21 on the top face of the semiconductor chip 20 areconnected to the leads 18 disposed around the TAB tape 17 and to the TABtape 17 via the wires 22. In FIG. 2, reference numerals 1 to 12 aregiven to the leads 18. The lead 18 having reference numeral 2 serves asan input terminal (Pin) and is electrically connected to the inputelectrode pad 25 of the semiconductor chip 20 via the wire 22. The lead18 having reference numeral 8 serves as an output terminal (Pout) and iselectrically connected to the output electrode pad 26 of thesemiconductor chip 20 via the wire 22.

[0078] The lead 18 having reference numeral 9 serves as a first powersource voltage terminal (Vdd) and is electrically connected to theelectrode pad 27 for first power source voltage of the semiconductorchip 20 via the wire 22. The lead 18 having reference numeral 4 servesas a third power source voltage terminal (Vgg) and is electricallyconnected to the electrode pad 29 for third power source voltage of thesemiconductor chip 20 via the wire 22. The electrode pad (GND) 28 forsecond power source voltage of the semiconductor chip 20 is electricallyconnected to the TAB tape 17 of the ground potential via the wire 22.

[0079] The plurality of electrode pads 21 and the TAB tape 17 providedfor the source electrode parts of the transistors 31 and 32 areelectrically connected to each other via the conductive wires 22. Theleads 18 having reference numerals 1, 3, 5, 6, 7, 10, 11, and 12 arenon-contact leads which are not used in the circuit. However, thenon-contact (NC) leads are used as terminals for mounting at the time ofmounting the power amplifier device 10 onto a mounting board.

[0080] In the structure, to make the inductance of the source electrodeclose to the inductance in the case of the via hole, the number of wiresconnected (metal lines each having a diameter of 25 μm) is set to themaximum number of six.

[0081] The transistor (HEMT), MIM capacitor, and inductance in thesemiconductor chip 20 will be described with reference to FIGS. 6 to 9.FIG. 6 is a schematic cross section showing an HEMT part, an MIMcapacitor part, and a spiral inductance part of the MMIC chip. FIG. 7 isa schematic enlarged cross section showing the HEMT part. FIG. 8 is aschematic enlarged cross section showing the MIM capacitor part and thespiral inductance part. FIG. 9 is an equivalent circuit diagram of theMIM capacitor.

[0082]FIG. 6 is a diagram in which the HEMT, MIM capacitor, andinductance are disposed in order from left to right for convenience ofdescription. It is assumed here that the transistor 31 is shown as theHEMT, the MIM capacitor 33 is shown as the MIM capacitor, and theinductance 34 is indicated as the inductance. Since these componentswill be described with reference to FIG. 7 or subsequent diagrams, theother reference numerals to FIG. 6 are omitted.

[0083] The semiconductor chip 20 is formed on a semi-insulating GaAssubstrate 85 as a base as shown in FIG. 7. On the top face (main face)side of the semi-insulating GaAs substrate 85, a GaAs epitaxial layer 86is formed. The transistor 31 portion has a structure in which ahigh-resistance buffer layer 87 made of AlGaAs, an undoped AlGaAs layer88, an n⁺-AlGaAs layer 89 of two layers as an electron supply layer, andan n⁺-GaAs layer 90 for obtaining ohmic contact are sequentially formedon the GaAs epitaxial layer 86. Near the junction between the AlGaAslayer 88 and the two n⁺-AlGaAs layers 89, a two-dimensional electronchannel 91 is formed. The buffer layer 87 plays the role of preventingleak current and preventing a short channel effect in an HEMT.

[0084] The HEMT formation region is etched to thereby form a mesaportion 92. The mesa etching reaches the surface layer of the GaAsepitaxial layer 86 through the buffer layer 87. The surface of the mesaportion 92 is covered with an insulating film 93 (an SiO₂ film 93 a andan SiN film 93 b), and the insulating film 93 is selectively etched. Byperforming etching with the residual insulating film 93 as a mask, atrench 94 extending through the n⁺-GaAs layer 90 and reaching thesurface layer of the two n⁺-AlGaAs layers 89 is formed in apredetermined pattern. In the first embodiment, the gate fingers 39 b ofthe gate (G) electrode 39 are provided on the trenches 94. Incorrespondence with FIG. 1, six trenches 94 are provided in parallelwith each other.

[0085] For example, the n⁺-GaAs layers 90 on both sides of the trench 94are used as drain and source regions. Therefore, the insulating film 93covering the top face of the n⁺-GaAs layer 90 is selectively removed andcontact holes are formed. In the contact holes, the drain fingers 37 bof the drain (D) electrode 37 or the source fingers 38 b of the source(S) electrode 38 are formed. The gate electrode 39 is made of Pt and thedrain and source electrodes 37 and 38 are made of AuGeNi. The thicknessof each of the drain and source electrodes 37 and 38 is about 0.38 μm.

[0086] The MIM capacitor 33 and the inductance 34 have a sectionstructure shown in FIG. 8. Specifically, in a region in which the MIMcapacitor 33 and the inductance 34 are formed, the buffer layer 87 andlayers upper than that are etched. On the GaAs epitaxial layer 86,insulating films 96 and 97 are stacked.

[0087] Reference numeral 100 in the MIM capacitor 33 portion in FIG. 8denotes a lower electrode formed on the insulating film 97. The lowerelectrode 100 extends to connect the MIM capacitor 33 and the inductance34 and serves as a line reaching the connection node A. A left endportion of the lower electrode 100 is covered with insulating films 101,102, and 103 selectively overlapped, and the top face of a part of thelower electrode 100 is exposed. A dielectric layer 104 forming acapacitance is selectively formed so as to be overlapped with theexposed portion. The periphery of the dielectric layer 104 extends evento the top face of the insulating film 102. A lead electrode 105overlapped on the top face of the dielectric layer 104, the top face andleft end faces of the insulting films 101 to 103 and, further, the topface of the insulating film 97 is formed. In such a manner, one of theMIM capacitors is formed. The lead electrode 105 is connected to theelectrode pad (Vgg) 29 for third power source voltage.

[0088] In a portion corresponding to the dielectric layer 104 of the topface of the lead electrode 105, an insulating film 106 is selectivelyformed, thereby forming a structure that the top face of the leadelectrode 105 is exposed. A dielectric layer 107 as a component of thecapacitor is selectively formed so as to overlap the exposed leadelectrode 105. The dielectric layer 107 extends also on the insulatingfilm 106 in the periphery. An upper electrode 108 is also formed so asto overlap on the top face of the dielectric layer 107, the top face andthe right end face of the insulating film 106, and right end faces ofthe insulting films 103 and 102. The upper electrode 108 is electricallyconnected to the lower electrode 100. By the above, another MIMcapacitor is formed. With the configuration, the MIM capacitor shown inthe equivalent circuit diagram of FIG. 9 is formed. The dielectriclayers 104 and 107 are formed by an SiO₂ film.

[0089] The inductance 34 is formed by a square-cornered spiral part 110as shown in FIGS. 8 and 1 (in FIG. 1, the reference numeral is notshown). The center of the spiral part 110 is electrically connected to alead electrode 111 formed on the top face of the GaAs epitaxial layer86. The lead electrode 111 passes under the insulating film 97 and islinked with the electrode pad (Vgg) 29 for third power source voltage.The outer end of the spiral part 110 is electrically connected to thelower electrode 100. A lower layer of the spiral part 110 is made of Moand an upper layer of the spiral part 110 is made of Au. The leadelectrode 111 is made of Al.

[0090] In the power amplifier device 10 of the first embodiment, thewidths of the source fingers 38 b of the source electrode 38 in the HEMTare set as shown in FIG. 10. Specifically, the width of each of fingerspositioned at both ends is set to be different from the width of each offingers positioned between the fingers positioned at both ends, and thewidth W3 of each of the source fingers 38 b at both ends is set to bewider (thicker) than the width W1 of each of the source fingers 38 bpositioned between both ends. The width W3 is equal to or wider than thesum of the widths W1 of the source fingers 38 b positioned between bothends. The width W2 of the source base portion 38 a of the sourceelectrode 38 is equal to or wider than the width W3.

[0091] The electrode patterns of the transistors 31 and 32 are symmetricwith respect to a line connecting the input electrode pad 25 with theoutput electrode pad 26 as shown in FIG. 2. In each of the transistors31 and 32, each of the fingers extends in the direction orthogonal tothe line connecting the input electrode pad 25 and the output electrodepad 26. With the arrangement, the top face of the semiconductor chip 20can be effectively used and miniaturization of the semiconductor chip 20can be achieved. Although not shown in FIG. 10, the electrode pad 21 isprovided for the source base portion 38 a. In the first embodiment, sixelectrode pads 21 are provided in a line (refer to FIG. 1).

[0092] To verify the effects in the electrode pattern shown in FIG. 10,an MMIC was experimentally manufactured and verified. In an MMIC havingthe FET electrode pattern shown in FIG. 17 and an MMIC having the FETelectrode pattern shown in FIG. 1, the number of source bonding wires ofan EFT (HEMT) was set (six wires each of which is a metal line having adiameter of 25 μm) so as to achieve the same inductance as that in thecase of forming via holes, and characteristics were compared. The gatewidth of the HEMT was set to 1.2 mm (the number of gate fingers wassix), the gate length was set to 0.4 μm, the gate finger width was setto 200 μm, the width W1 of the source finger 38 b on the inner side(between terminals) was set to 20 μm, the width W3 of the source finger38 b at an end was set to 60 μm, and the width W4 of the drain finger 37b was set to 20 μm.

[0093] Evaluation conditions are Vdd=5V, and Id=120 mA at 5.2 GHz. Theresult is as shown in Table 1. Items of The present Conventionalcharacteristics Invention Configuration gain (dB) 8.7 7.6 P1dB (dBm)26.0 25.0 width w1/w3 (μm) 20/60 20/—

[0094] In the power amplifier device 10 of the first embodiment, thegain is improved by 1.1 dB from 7.6 dB of the conventional configurationto 8.7 dB of the first embodiment. At P1dB (output power when the gaindrops from a small signal gain by 1 dB), improvement in performance of 1dBm can be recognized. Therefore, the number of wires can be reduced byan amount corresponding to the improvement in performance, andminiaturization of the semiconductor chip (chip shrink) can be realized.

[0095] The improvement in performance of the power amplifier device 10,that is, an HEMT device will be, though qualitatively, described withreference to FIG. 11. A drain current Id indicates the sum of currentsIdi (i=1, 2, 3, 4, 5, 6) of unit gates. Although the currents Idi ofunit gates are ideally the same, generally, the current value in thecase where gates are arranged cyclically is large in a center portionwhere the electric field is concentrated and decreases toward the ends.Because of symmetry, Id3=Id4, Id2=Id5, and Id1=Id6.

[0096] Therefore, the following equation is obtained.

Id3=Id4>Id2=Id5>Id1=Id6  Equation 1

[0097] As understood from Equation 1, by making the electrode on theouter side thicker (wider), electric field concentration in the centerportion is lessened, and the currents Id1 and Id6 in the peripheralportion can be increased to almost the same as the currents Id3 and Id4in the center portion. It can also be considered that the performance ofthe device is improved by increase in current.

[0098] In manufacture of the semiconductor chip 20 (MMIC chip) of thefirst embodiment shown in FIG. 1, as compared with manufacture using viaholes, about five masks can be reduced. Moreover, there is nohigh-precision back face processing, so that the process can beshortened by about three weeks and reduction in manufacturing cost canbe achieved. The thickness of a substrate (semi-insulating GaAssubstrate) used for manufacture is as thick as about 150 μm, so that itis unnecessary to reduce the thickness. Consequently, there is noproblem such as deterioration in handling, and workability improves.

[0099] The first embodiment has the following effects.

[0100] (1) In the first embodiment, in the source fingers 38 b and 43 barranged in a comb-teeth shape, of the source electrodes 38 and 43 asearth electrodes of an HEMT, the electrode width W3 of each of thesource fingers 38 b and 43 b positioned at both ends is set to be wider(thicker) than the electrode width W1 of each of the source fingers 38 band 43 b positioned between both ends. Consequently, electric fieldconcentration on each of the source fingers 38 b and 43 b in the centerportion is lessened, current in the source fingers 38 b and 43 bpositioned at both ends can be increased, and the performance (highfrequency characteristic) of the device improves. The electrode width W3of each of the source fingers 48 b and 43 b positioned at both ends isset to be equal to or wider than the sum of the widths W1 of the sourcefingers 38 b and 43 b positioned between both ends. Thus, concentrationof the electric field in the source fingers 38 b and 43 b in the centerportion is lessened, and increase in current in the source fingers 38 band 43 b positioned at both ends can be achieved.

[0101] In the invention, also in an HEMT single body, that is, in asemiconductor device, the electrode width W3 of each of the sourcefingers positioned at both ends is set to be wider than the electrodewidth W1 of each of the source fingers positioned at both ends, so thatconcentration of the electric field in each of the source fingers in thecenter portion is lessened, current can be increased in the sourcefingers positioned at both ends, and the performance of the device (highfrequency characteristic) is improved. The electrode width W3 of each ofthe source fingers positioned at both ends is set to be wider than thesum of the widths W1 of the source fingers positioned between both ends.Consequently, concentration of the electric field in the source fingersin the center portion is lessened, and increase in current in the sourcefingers positioned at both ends can be achieved.

[0102] (2) In the power amplifier device 10 of the first embodiment,power is output so as to reduce a current difference due to a potentialdifference in each of the positions of each of the plurality of drainfingers 37 b and 42 b of the output electrodes (drain electrodes 37 and42) in the built-in transistors 31 and 32 (HEMTs) and so as to causeohmic resistance of the earth electrodes (source electrodes 38 and 43),and the electrode width W2 of each of the common earth electrodes(source base portions 38 a and 43 a) for commonly connecting theplurality of earth electrode fingers (source fingers 38 b and 43 b) isset to be wider than the electrode width W3 of the source fingers 38 band 43 b positioned at both ends. Thus, power loss can be reduced.

[0103] (3) The electrode patterns of the transistors 31 and 32 aresymmetric with respect to the line connecting the input electrode pad 25and the output electrode pad 26. In each of the transistors 31 and 32,each of the fingers extends in the direction orthogonal to the lineconnecting the input electrode pad 25 and the output electrode pad 26.With the arrangement, the top face of the semiconductor chip 20 can beeffectively used and miniaturization of the semiconductor chip 20 can beachieved.

[0104] (4) In the power amplifier device 10 of the first embodiment, inmanufacture of the semiconductor chip 20 (MMIC chip), as compared withmanufacture using via holes, about five masks can be reduced. Sincethere is no high-precision back face processing, the process of aboutthree weeks can be shortened and reduction in manufacturing cost can beachieved.

[0105] (5) In manufacture of the power amplifier device 10 of the firstembodiment, the thickness of a substrate (semi-insulating GaAssubstrate) used for manufacture is as thick as about 150 μm, so that itis unnecessary to reduce the thickness. Consequently, there is noproblem such as deterioration in handling, and workability improves. Itcan reduce the manufacturing cost of the power amplifier device 10.

[0106] (6) From (1) to (5), according to the embodiment, the small andcheap power amplifier device having excellent high frequencycharacteristics and high performance (little power loss) can beprovided.

[0107] (7) By assembling the high-performance small power amplifierdevice having excellent high frequency characteristics, a personalcomputer card having excellent characteristics can be provided. The sizeof the personal computer can also be reduced.

[0108] (Second Embodiment)

[0109]FIGS. 14 and 15 are diagrams of a power amplifier device asanother embodiment (second embodiment) of the invention. Although anHEMT is assembled as a transistor in the semiconductor chip 20 (notshown) in the first embodiment, an HBT as a bipolar transistor isassembled in the semiconductor chip 20 in the second embodiment. FIG. 14is a diagram showing a transistor part in the semiconductor chip 20.

[0110] In the second embodiment as well, to increase an output, astructure in which transistors (HBTs) 141 and 142 are connected inparallel in a manner similar to the first embodiment is employed. InFIG. 14, the transistor 141 is positioned in the upper stage and thetransistor 142 is positioned in the lower stage. The transistors 141 and142 are symmetrical with each other in the vertical direction.Therefore, corresponding components in the transistors 141 and 142 willbe described by use of the same names and the same reference numerals.

[0111] Each of the transistors 141 and 142 has an emitter (E) electrode,a base (B) electrode, and a collector (C) electrode. In the secondembodiment, a common emitter structure is employed. The electrodepattern of each of the HBTs 141 and 142 has, as shown in FIG. 14, likethe electrode pattern of the HEMT of the first embodiment, a comb-shapedelectrode structure. An emitter electrode 123, a base electrode 128, anda collector electrode 127 have a comb-teeth pattern constructed by baseportions 123 a, 128 a, and 127 a and a plurality of fingers 123 b, 128b, and 127 b extended from the base portions. In the case of the secondembodiment, although not limited, an HBT structure is formed in such amanner that the plurality of collector fingers 127 b are projected fromboth sides of the base portion 127 a of the collector electrode 127 andthe base fingers 128 b and the emitter fingers 123 b mesh with thecollector fingers 127 b.

[0112] The base fingers 128 b extend so as to surround the collectorfingers 127 b with a small gap and so as not to be arranged in a ringshape. Each of the emitter fingers 123 b projecting from the emitterbase portion 123 a is forked at some midpoint into two portions and thetwo portions extend so as to sandwich the base finger 128 b with a smallgap.

[0113] Each of the HBTs 141 and 142 has a pattern in which, to increaseoutput, the plurality of collector fingers 127 b are projected from bothsides of the collector base portion 127 a. Consequently, the emitterelectrode 123 and the base electrode 128 are disposed on each of bothsides of the collector base portion 127 a extending in the verticaldirection in FIG. 14.

[0114] The base portion 128 a of the base electrode 128 is connected toa lead electrode 128 e for the base. The number of lead electrodes 128 efor the base finally becomes one and is led to the left side as shown inFIG. 14. The lead electrode 128 e for the base is connected to the MIMcapacitor 33 and the inductance 34 in the first embodiment. Thecollector base portions 127 a of the HBTs 141 and 142 are connected to alead electrode 127 e for the collector. The lead electrode 127 e for thecollector is led to the right side as shown in FIG. 14. The leadelectrode 127 e for the collector is connected to the first power sourcevoltage terminal (Vdd) 27 and the MIM capacitor 35 in the firstembodiment.

[0115] A plurality of electrode pads 145 are provided for the emitterbase portion 123 a of the emitter electrode 123. To the electrode pad145, the wire 22 connected to the TAB tape 17 is connected in a mannersimilar to the first embodiment.

[0116] The structure in a section taken along line A-A′ of FIG. 14 as afinger portion will be described with reference to FIG. 15. An HBT has,as shown in FIG. 15, a structure in which an n-sub emitter layer 121made of n⁺-GaAs is selectively provided on the top face (main face) of asemi-insulating GaAs substrate 120. An n-GaAs emitter layer 122 isselectively formed on the top face of the n-sub emitter layer 121. Onthe top face of the n-sub emitter layer 121 around the n-GaAs emitterlayer 122, an emitter electrode 123 (emitter fingers 123 b) made of AuGeis formed.

[0117] A p⁺GaAs layer 124 is formed on the top face of the n-GaAsemitter layer 122, and an n-GaAs base layer 125 is provided on thep⁺GaAs layer 124. An n-InGaP collector layer 126 is formed in the centerportion of the top face of the n-GaAs base layer 125. On the top face ofthe n-InGaP collector layer 126, the collector electrode 127 (collectorfingers 127 b) made of WSi is provided. On the top face of the n-GaAsbase layer 125 around the n-InGaP collector layer 126, the baseelectrode 128 (base fingers 128 b) made of Pt is provided.

[0118] The main face side of the semi-insulating GaAs substrate 120 iscovered with an insulating film 129. With the insulating film 129, theemitter electrode 123 (emitter fingers 123 b), n-GaAs emitter layer 122,p⁺GaAs layer 124, n-GaAs base layer 125, base fingers 128 b, n-InGaPcollector layer 126, and collector fingers 127 b are covered.

[0119] Also in the earth electrode (emitter electrode 123) in each ofthe transistors (HBTs) 141 and 142 in the second embodiment, in a mannersimilar to the first embodiment, the width W3 of each of the fingerspositioned at both ends of the emitter fingers 123 b is wider than thewidth W1 of each of the fingers positioned between both ends and isequal to or larger than the sum of the widths W1 of the fingerspositioned between both ends. With the configuration, in a mannersimilar to the first embodiment, concentration of the electric field ineach of the emitter fingers 123 b in the center portion is lessened, thecurrent can be increased in the emitter fingers 123 b positioned at bothends, and the performance (high frequency characteristics) of the deviceis improved. Since the width W2 of the emitter base portion 123 a isequal to or wider than the width W3, power loss can be reduced.

[0120] Although the invention achieved by the inventor herein has beenconcretely described above on the basis of the embodiments, obviously,the invention is not limited to the foregoing embodiments but may bevariously changed without departing from the gist. Specifically,although the examples of using an HEMT or an HBT as a transistor havebeen described in the embodiments, effects similar to those of theforegoing embodiments can also be obtained by a case using anothertransistor such as Si-GeFET or MOSFET.

[0121] Although one amplification system is provided in the poweramplifier device of each of the embodiments, the invention can belikewise applied to a device having a plurality of amplification systemsand effects similar to those of the embodiments can be obtained.

[0122] Effects obtained by a representative one of the inventionsdisclosed in the specification will be briefly described as follows.

[0123] (1) By reduction in inductance of the earth electrode, the highfrequency characteristics of the power amplifier device can be improved.

[0124] (2) The manufacturing cost of the power amplifier device can bereduced.

[0125] (3) A personal computer card having excellent high frequencycharacteristics can be provided.

What is claimed is:
 1. A semiconductor device having a semiconductorchip formed with a transistor, wherein said transistor has a firstelectrode, a second electrode, and a control electrode, wherein each ofsaid first and second electrodes is constructed by a base portion and aplurality of fingers projected in a direction orthogonal to said baseportion, wherein one of the fingers of said first electrode is disposedbetween neighboring two fingers of said second electrode, wherein saidsecond electrode is connected to a fixed potential, and wherein a widthof each of said fingers positioned at both ends of said second electrodeis wider than a width of each of said fingers positioned between saidboth ends.
 2. The semiconductor device according to claim 1, wherein thewidth of each of said fingers positioned at both ends is equal to orwider than a sum of the widths of said plurality of fingers positionedbetween said both ends.
 3. The semiconductor device according to claim1, wherein the width of said base portion of said second electrode iswider than the width of each of said fingers positioned at both ends. 4.The semiconductor device according to claim 1, wherein said firstelectrode is a drain electrode, said second electrode is a sourceelectrode, and said control electrode is a gate electrode.
 5. Thesemiconductor device according to claim 1, wherein said first electrodeis a collector electrode, said second electrode is an emitter electrode,and said control electrode is a base electrode.
 6. The semiconductordevice according to claim 1, wherein said base portions of saidelectrodes extend in the same direction, and said fingers of saidelectrodes extend in a direction orthogonal to an extending direction ofsaid base portions.
 7. A power amplifier device having one or aplurality of amplification systems, wherein said amplification systemhas a semiconductor chip in which a transistor is formed and a pluralityof external electrode terminals, wherein said external electrodeterminals are an input terminal to which a signal to be amplified issupplied, an output terminal for outputting the amplified signal, andfirst, second, and third power source terminals, wherein said transistoris electrically connected between said input terminal and said outputterminal, wherein electrodes of said transistor are a control electrodeconnected to said input terminal and said third power source terminal, afirst electrode connected to said output terminal and said first powersource terminal, and a second electrode connected to said second powersource terminal serving as an earth terminal, wherein over a top face ofsaid semiconductor chip, an electrode pad corresponding to said externalelectrode terminal and a plurality of electrode pads formed in a portionof said second electrode of said transistor are provided, wherein aconductive wire for electrically connecting said external electrodeterminal with said electrode pad corresponding to the external electrodeterminal, and a conductive wire for electrically connecting theplurality of electrode pads formed in the portion of said secondelectrode of said transistor with said second power source terminal areprovided, wherein each of said electrodes of said transistor isconstructed by a base portion and a plurality of fingers projected in adirection orthogonal to said base portion, one of the fingers of saidfirst electrode is disposed between two neighboring fingers of saidsecond electrode, wherein said second electrode is connected to a fixedpotential, and wherein a width of each of said fingers positioned atboth ends of said second electrode is wider than a width of each of saidfingers positioned between said both ends.
 8. The power amplifier deviceaccording to claim 7, wherein the width of each of said fingerspositioned at both ends is equal to or wider than a sum of the widths ofsaid plurality of fingers positioned between said both ends.
 9. Thepower amplifier device according to claim 7, wherein the width of saidbase portion of said second electrode is wider than the width of each ofsaid fingers positioned at both ends.
 10. The power amplifier deviceaccording to claim 7, wherein said first electrode is a drain electrode,said second electrode is a source electrode, and said control electrodeis a gate electrode.
 11. The power amplifier device according to claim7, wherein said first electrode is a collector electrode, said secondelectrode is an emitter electrode, and said control electrode is a baseelectrode.
 12. The power amplifier device according to claim 7, whereintwo transistors are formed in said semiconductor chip and areelectrically connected in parallel with each other between said inputterminal and said output terminal.
 13. The power amplifier deviceaccording to claim 7, further comprising: a supporting substratemounting said semiconductor chip and constructing said second powersource terminal; a plurality of leads disposed around said supportingsubstrate and constructing said external electrode terminals; and asealing part made of an insulating resin for covering said supportingsubstrate, said external electrode terminal, said semiconductor chip,and said wire in a state where an under face and an external end face ofeach of said supporting substrate and said external electrode terminalare exposed.
 14. The power amplifier device according to claim 13,wherein said sealing part has a square shape in plan view, and anexternal end face of said external electrode terminal is flush with aperipheral face of said sealing part.
 15. The power amplifier deviceaccording to claim 7, wherein a plurality of transistors are cascadedbetween said input terminal and said output terminal to therebyobtaining a multi-stage amplification configuration.
 16. The poweramplifier device according to claim 7, wherein said base portions ofsaid electrodes of said transistor extend in the same direction, saidfingers of said electrodes extend in a direction orthogonal to anextending direction of each of said base portions, and each of saidfingers extends in a direction orthogonal to a line connecting saidinput terminal with said output terminal.
 17. The power amplifier deviceaccording to claim 7, wherein said power amplifier device is a poweramplifier device for a wireless LAN of a 5-GHz band.
 18. A personalcomputer card having a power amplifier device for transmission connectedto an antenna, wherein said power amplifier device has the configurationof claim
 7. 19. The personal computer card according to claim 18,comprising: a transmission/reception change-over switch connected tosaid antenna; a low-noise amplifier for reception connected to saidtransmission/reception change-over switch; a reception-system mixerconnected to said low-noise amplifier for reception; a base band LSIconnected to said reception-system mixer; a transmission-system mixerconnected to said base band LSI; and a voltage controlled oscillatorconnected to said base band LSI, said reception-system mixer, and saidtransmission-system mixer, wherein said power amplifier device fortransmission is connected to said transmission-system mixer and saidtransmission/reception change-over switch.